Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9190479 | Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another | Jean-Olivier Plouchart, Alberto Valdes-Garcia | 2015-11-17 |
| 8877606 | Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation | Robert H. Dennard, Amlan Majumdar, Leathen Shi, Jeng-Bang Yau | 2014-11-04 |
| 8872279 | Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another | Jean-Olivier Plouchart, Alberto Valdes-Garcia | 2014-10-28 |
| 8455924 | Multi-level interconnections for an integrated circuit chip | John J. Pekarik, Jorg Scholvin | 2013-06-04 |
| 8421478 | Radio frequency integrated circuit with on-chip noise source for self-test | Brian A. Floyd, Ramana Malladi, Bradley A. Orner, Scott K. Reynolds | 2013-04-16 |
| 8227865 | Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer | Robert H. Dennard, Amlan Majumdar, Leathen She, Jeng-Bang Yau | 2012-07-24 |
| 8178908 | Electrical contact structure having multiple metal interconnect levels staggering one another | Jean-Olivier Plouchart, Alberto Valdes-Garcia | 2012-05-15 |
| 7767546 | Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer | Robert H. Dennard, Amian Majumdar, Leathen Shi, Jeng-Bang Yau | 2010-08-03 |
| 7713829 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology | Jack O. Chu, Douglas D. Coolbaugh, James S. Dunn, David L. Harame, Basanth Jagannathan +4 more | 2010-05-11 |
| 7642569 | Transistor structure with minimized parasitics and method of fabricating the same | Shwu-Jen Jeng | 2010-01-05 |
| 7615457 | Method of fabricating self-aligned bipolar transistor having tapered collector | Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, Marwan H. Khater, William R. Tonti | 2009-11-10 |
| 7491617 | Transistor structure with minimized parasitics and method of fabricating the same | Shwu-Jen Jeng | 2009-02-17 |
| 7425754 | Structure and method of self-aligned bipolar transistor having tapered collector | Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, Marwan H. Khater, William R. Tonti | 2008-09-16 |
| 7414275 | Multi-level interconnections for an integrated circuit chip | John J. Pekarik, Jorg Scholvin | 2008-08-19 |
| 7355221 | Field effect transistor having an asymmetrically stressed channel region | Gregory G. Freeman, Anil K. Chinthakindi, Basanth Jagannathan, Marwan H. Khater, John J. Pekarik +1 more | 2008-04-08 |
| 7253070 | Transistor structure with minimized parasitics and method of fabricating the same | Shwu-Jen Jeng | 2007-08-07 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology | Jack O. Chu, Douglas D. Coolbaugh, James S. Dunn, David L. Harame, Basanth Jagannathan +4 more | 2007-02-06 |
| 7075126 | Transistor structure with minimized parasitics and method of fabricating the same | Shwu-Jen Jeng | 2006-07-11 |
| 6836029 | Micro-electromechanical switch having a conductive compressible electrode | Hariklia Deligianni, Robert A. Groves, Christopher V. Jahnes, Jennifer Lund, Katherine L. Saenger +1 more | 2004-12-28 |
| 6815802 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology | Jack O. Chu, Douglass Duane Coolbaugh, James S. Dunn, David L. Harame, Basanth Jagannathan +4 more | 2004-11-09 |
| 6787427 | Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics | Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell | 2004-09-07 |
| 6656809 | Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics | Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell | 2003-12-02 |
| 6531720 | Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors | Gregory G. Freeman, Shwu-Jen Jeng | 2003-03-11 |
| 6429500 | Semiconductor pin diode for high frequency applications | Kathryn T. Schonenberg, Seshadri Subbanna, Keith M. Walter | 2002-08-06 |
| 6426265 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology | Jack O. Chu, Douglas D. Coolbaugh, James S. Dunn, David L. Harame, Basanth Jagannathan +4 more | 2002-07-30 |