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CMOS transistor with a polysilicon gate electrode having varying grain size |
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2010-05-11 |
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Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size |
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Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics |
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| 6670263 |
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size |
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2003-12-30 |
| 6656809 |
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics |
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2003-12-02 |
| 5899724 |
Method for fabricating a titanium resistor |
David M. Dobuzinsky, Stephen G. Fugardi, Erwin Hammerl, Herbert L. Ho, Alvin W. Strong |
1999-05-04 |
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures |
Herbert L. Ho, Erwin Hammerl, David M. Dobuzinsky, Herbert Palm, Stephen G. Fugardi +2 more |
1998-05-05 |
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures |
Herbert L. Ho, Erwin Hammerl, David M. Dobuzinsky, J. Herbert Palm, Stephen G. Fugardi +2 more |
1997-07-01 |
