Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7714366 | CMOS transistor with a polysilicon gate electrode having varying grain size | Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles +3 more | 2010-05-11 |
| 6893948 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles +3 more | 2005-05-17 |
| 6787427 | Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics | David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, David M. Rockwell | 2004-09-07 |
| 6670263 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles +3 more | 2003-12-30 |
| 6656809 | Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics | David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, David M. Rockwell | 2003-12-02 |
| 5899724 | Method for fabricating a titanium resistor | David M. Dobuzinsky, Stephen G. Fugardi, Erwin Hammerl, Herbert L. Ho, Alvin W. Strong | 1999-05-04 |
| 5747866 | Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures | Herbert L. Ho, Erwin Hammerl, David M. Dobuzinsky, Herbert Palm, Stephen G. Fugardi +2 more | 1998-05-05 |
| 5643823 | Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures | Herbert L. Ho, Erwin Hammerl, David M. Dobuzinsky, J. Herbert Palm, Stephen G. Fugardi +2 more | 1997-07-01 |