Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7714366 | CMOS transistor with a polysilicon gate electrode having varying grain size | Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Glen L. Miles, James J. Quinlivan +3 more | 2010-05-11 |
| 6893948 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Glen L. Miles, James J. Quinlivan +3 more | 2005-05-17 |
| 6670263 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Glen L. Miles, James J. Quinlivan +3 more | 2003-12-30 |
| 6504207 | Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same | Bomy Chen, Jay G. Harrington, Dennis Hoyniak, Chung H. Lam, Hyun Koo Lee +2 more | 2003-01-07 |
| 6342431 | Method for eliminating transfer gate sacrificial oxide | Jed H. Rankin | 2002-01-29 |
| 6326275 | DRAM cell with vertical CMOS transistor | Jay G. Harrington, David V. Horak, Chung H. Lam, Rebecca D. Mih | 2001-12-04 |
| 6258673 | Multiple thickness of gate oxide | Liang Han, Dale W. Martin | 2001-07-10 |