Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9355936 | Flattened substrate surface for substrate bonding | Edward C. Cooney, III, James S. Dunn, Charles S. Musante, BethAnn Rainey Lawrence, Leathen Shi +2 more | 2016-05-31 |
| 9165819 | High linearity SOI wafer for low-distortion circuit applications | Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Gerd Pfeiffer +1 more | 2015-10-20 |
| 8951896 | High linearity SOI wafer for low-distortion circuit applications | Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Gerd Pfeiffer +1 more | 2015-02-10 |
| 8778737 | Flattened substrate surface for substrate bonding | Edward C. Cooney, III, James S. Dunn, Charles F. Musante, BethAnn Rainey, Leathen Shi +2 more | 2014-07-15 |
| 8679863 | Fine tuning highly resistive substrate resistivity and structures thereof | Jeffrey P. Gambino, Derrick Liu, Gerd Pfeiffer | 2014-03-25 |
| 7883990 | High resistivity SOI base wafer using thermally annealed substrate | Max G. Levy, Gerd Pfeiffer, James A. Slinkman | 2011-02-08 |
| 7446007 | Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof | James W. Adkisson, Marc W. Cantell, James R. Elliott, James V. Hart, III | 2008-11-04 |
| 7378712 | Gate stacks | Steven M. Shank, Michael C. Triplett, Deborah A. Tucker | 2008-05-27 |
| 7303952 | Method for fabricating doped polysilicon lines | James W. Adkisson, John J. Ellis-Monaghan, Glenn C. MacDougall, Kirk D. Peterson, Bruce W. Porth | 2007-12-04 |
| 7190007 | Isolated fully depleted silicon-on-insulator regions by selective etch | Matthew J. Breitwisch, Chung H. Lam, Randy W. Mann | 2007-03-13 |
| 7157341 | Gate stacks | Steven M. Shank, Michael C. Triplett, Deborah A. Tucker | 2007-01-02 |
| 6949458 | Self-aligned contact areas for sidewall image transfer formed conductors | Edward W. Conrad, Chung H. Lam, Edmund J. Sprogis | 2005-09-27 |
| 6610607 | Method to define and tailor process limited lithographic features using a modified hard mask process | Douglas S. Armbrust, Jed H. Rankin, Sylvia Tousley | 2003-08-26 |
| 6566759 | Self-aligned contact areas for sidewall image transfer formed conductors | Edward W. Conrad, Chung H. Lam, Edmund J. Sprogis | 2003-05-20 |
| 6525371 | Self-aligned non-volatile random access memory cell and process to make the same | Jeffrey B. Johnson, Chung H. Lam, Dana Lee, Jed H. Rankin | 2003-02-25 |
| 6486510 | Reduction of reverse short channel effects by implantation of neutral dopants | Jeffrey S. Brown, Stephen Furkay, Robert J. Gauthier, Jr., James A. Slinkman | 2002-11-26 |
| 6352912 | Reduction of reverse short channel effects by deep implantation of neutral dopants | Jeffrey S. Brown, Stephen Furkay, Robert J. Gauthier, Jr., James A. Slinkman | 2002-03-05 |
| 6294429 | Method of forming a point on a floating gate for electron injection | Chung H. Lam, Christa R. Willets | 2001-09-25 |
| 6258673 | Multiple thickness of gate oxide | Kevin M. Houlihan, Liang Han | 2001-07-10 |
| 6197632 | Method for dual sidewall oxidation in high density, high performance DRAMS | Gary B. Bronner, Rama Divakaruni, Scott D. Halle, Rajesh Rengarajan, Mary E. Weybright | 2001-03-06 |
| 5972765 | Use of deuterated materials in semiconductor processing | William F. Clark, Jr., Thomas G. Ference, Terence B. Hook | 1999-10-26 |
| 5926708 | Method for providing multiple gate oxide thicknesses on the same wafer | — | 1999-07-20 |
| D307153 | Viewer for a door | — | 1990-04-10 |