| RE49794 |
SRAM design to facilitate single fin cut in double sidewall image transfer process |
Robert C. Wong |
2024-01-09 |
|
| 10096521 |
SRAM design to facilitate single fin cut in double sidewall image transfer process |
Robert C. Wong |
2018-10-09 |
$3,566,000 |
| 9564446 |
SRAM design to facilitate single fin cut in double sidewall image transfer process |
Robert C. Wong |
2017-02-07 |
$2,910,000 |
| 6930004 |
Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling |
Geng Wang, Kevin McStay, Yujun Li, Dureseti Chidambarrao |
2005-08-16 |
$6,237,000 |
| 6724053 |
PMOSFET device with localized nitrogen sidewall implantation |
Rama Divakaruni, Ryota Katsumata, Giuseppe La Rosa, Rajesh Rengarajan |
2004-04-20 |
$6,170,000 |
| 6670667 |
Asymmetric gates for high density DRAM |
Ramachandra Divakaruni, Wayne F. Ellis, Jack A. Mandelman |
2003-12-30 |
$8,971,000 |
| 6656798 |
Gate processing method with reduced gate oxide corner and edge thinning |
Helmut Tews, Oleg Gluschenkov |
2003-12-02 |
$319,000 |
| 6548357 |
Modified gate processing for optimized definition of array and logic devices on same chip |
Gary B. Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more |
2003-04-15 |
|
| 6504210 |
Fully encapsulated damascene gates for Gigabit DRAMs |
Ramachandra Divakaruni, Jeffrey P. Gambino, Jack A. Mandelman, Viraj Y. Sardesai |
2003-01-07 |
$16,905,000 |
| 6458646 |
Asymmetric gates for high density DRAM |
Ramachandra Divakaruni, Wayne F. Ellis, Jack A. Mandelman |
2002-10-01 |
$10,556,000 |
| 6403423 |
Modified gate processing for optimized definition of array and logic devices on same chip |
Gary B. Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more |
2002-06-11 |
$11,523,000 |
| 6388294 |
Integrated circuit using damascene gate structure |
Carl Radens, Gary B. Bronner |
2002-05-14 |
$14,429,000 |
| 6380027 |
Dual tox trench dram structures and process using V-groove |
Toshiharu Furukawa, Jeffrey P. Gambino, Edward W. Kiewra, Jack A. Mandelman, Carl Radens +1 more |
2002-04-30 |
$15,490,000 |
| 6346734 |
Modified gate conductor processing for poly length control in high density DRAMS |
Ramachandra Divakaruni |
2002-02-12 |
$23,472,000 |
| 6326260 |
Gate prespacers for high density, high performance DRAMs |
Ramachandra Divakaruni, James W. Adkisson, Scott D. Halle, Jeffrey P. Gambino, Heon Lee |
2001-12-04 |
$28,474,000 |
| 6261972 |
Dual gate oxide process for uniform oxide thickness |
Helmut Tews, Stephan Kudelka, Oleg Gluschenkov, Suri Hegde |
2001-07-17 |
|
| 6197632 |
Method for dual sidewall oxidation in high density, high performance DRAMS |
Gary B. Bronner, Rama Divakaruni, Scott D. Halle, Dale W. Martin, Rajesh Rengarajan |
2001-03-06 |
$28,649,000 |
| 6194301 |
Method of fabricating an integrated circuit of logic and memory using damascene gate structure |
Carl Radens, Gary B. Bronner |
2001-02-27 |
$24,775,000 |
| 6190979 |
Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill |
Carl Radens |
2001-02-20 |
$23,750,000 |
| 6180975 |
Depletion strap semiconductor memory device |
Carl Radens |
2001-01-30 |
$13,187,000 |
| 6096664 |
Method of manufacturing semiconductor structures including a pair of MOSFETs |
Thomas Rupp, Stephan Kudelka, Jeffrey P. Gambino |
2000-08-01 |
$27,147,000 |
