Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12310139 | Semiconductor devices with single-photon avalanche diodes and isolation structures | Jeffrey P. Gambino, David T. Price, Marc Sulfridge, Richard A. Mauritzson, Michael Gerard KEYES +1 more | 2025-05-20 |
| 12034025 | Semiconductor devices with single-photon avalanche diodes and isolation structures | Jeffrey P. Gambino, David T. Price, Marc Sulfridge, Richard A. Mauritzson, Michael Gerard KEYES +1 more | 2024-07-09 |
| 9484269 | Structure and method to control bottom corner threshold in an SOI device | Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang +1 more | 2016-11-01 |
| 9437496 | Merged source drain epitaxy | Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Shreesh Narasimha, Chengwen Pei +1 more | 2016-09-06 |
| 8809953 | FET structures with trench implantation to improve back channel leakage and body resistance | David M. Fried, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Gan Wang +2 more | 2014-08-19 |
| 8395217 | Isolation in CMOSFET devices utilizing buried air bags | Kangguo Cheng, Joseph Ervin, Jeffrey B. Johnson, Pranita Kulkarni, Paul C. Parries +3 more | 2013-03-12 |
| 8236632 | FET structures with trench implantation to improve back channel leakage and body resistance | David M. Fried, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Gan Wang +2 more | 2012-08-07 |
| 8232603 | Gated diode structure and method including relaxed liner | Anthony I. Chou, Gregory G. Freeman, Shreesh Narasimha | 2012-07-31 |
| 7989298 | Transistor having V-shaped embedded stressor | Kevin K. Chan, Brian J. Greene, Judson R. Holt, Jeffrey B. Johnson, Thomas S. Kanarsky +4 more | 2011-08-02 |
| 7733109 | Test structure for resistive open detection using voltage contrast inspection and related methods | Ishtiaq Ahsan, Mark B. Ketchen, Oliver D. Patterson | 2010-06-08 |
| 6930004 | Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling | Geng Wang, Mary E. Weybright, Yujun Li, Dureseti Chidambarrao | 2005-08-16 |
| 6740920 | Vertical MOSFET with horizontally graded channel doping | Dureseti Chidambarrao, Kil-Ho Lee, Jack A. Mandelman, Rajesh Rengarajan | 2004-05-25 |
| 6693843 | Wordline on and off voltage compensation circuit based on the array device threshold voltage | Thomas M. Maffitt, Russell J. Houghton, Mark D. Jacunski, William R. Tonti | 2004-02-17 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping | Dureseti Chidambarrao, Ramachandra Divakaruni, Jack A. Mandelman | 2003-06-03 |
| 6381182 | Combined tracking of WLL and VPP low threshold voltage in DRAM array | — | 2002-04-30 |