MJ

Mark D. Jacunski

IBM: 16 patents #6,952 of 70,183Top 10%
Globalfoundries: 4 patents #817 of 4,424Top 20%
Infineon Technologies Ag: 2 patents #4,439 of 7,486Top 60%
Disney: 1 patents #3,944 of 6,686Top 60%
Overall (All Time): #203,175 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
RE50596 On-chip reliability monitor and method John A. Fifield, Eric D. Hunt-Schroeder 2025-09-23
10535379 Latching current sensing amplifier for memory array Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder 2020-01-14
10429434 On-chip reliability monitor and method John A. Fifield, Eric D. Hunt-Schroeder 2019-10-01
10020047 Static random access memory (SRAM) write assist circuit with improved boost Eric D. Hunt-Schroeder, John A. Fifield 2018-07-10
9870979 Double-sided segmented line architecture in 3D integration Pooja R. Batra, John W. Golz, Toshiaki Kirihata 2018-01-16
9779783 Latching current sensing amplifier for memory array Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder 2017-10-03
9559040 Double-sided segmented line architecture in 3D integration Pooja R. Batra, John W. Golz, Toshiaki Kirihata 2017-01-31
9093175 Signal margin centering for single-ended eDRAM sense amplifier John E. Barth, Jr., John A. Fifield 2015-07-28
8902679 Memory array with on and off-state wordline voltages having different temperature coefficients John A. Fifield 2014-12-02
8649239 Multi-bank random access memory structure with global and local signal buffering for improved performance Darren L. Anand, John A. Fifield, Matthew Christopher Lanahan 2014-02-11
7221601 Timer lockout circuit for synchronous applications Alan D. Norris, Samuel Weinstein 2007-05-22
7194670 Command multiplier for built-in-self-test Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Toshiaki Kirihata, Alan D. Norris +2 more 2007-03-20
7085180 Method and structure for enabling a redundancy allocation during a multi-bank operation Gregory J. Fredeman, Toshiaki Kirihata, Matthew R. Wordeman 2006-08-01
7068564 Timer lockout circuit for synchronous applications Alan D. Norris, Samuel Weinstein 2006-06-27
6693843 Wordline on and off voltage compensation circuit based on the array device threshold voltage Thomas M. Maffitt, Russell J. Houghton, William R. Tonti, Kevin McStay 2004-02-17
6580650 DRAM word line voltage control to insure full cell writeback level Wayne F. Ellis, Russell J. Houghton, Thomas M. Maffitt, William R. Tonti 2003-06-17
6580655 Pre-charge circuit and method for memory devices with shared sense amplifiers Michael Killian 2003-06-17
6522154 Oxide tracking voltage reference John A. Fifield, Thomas M. Maffitt, Nicholas Heel 2003-02-18
6399990 Isolated well ESD device Ciaran J. Brennan, Michael Killian, William R. Tonti 2002-06-04
6400202 Programmable delay element and synchronous DRAM using the same John A. Fifield, Nicholas M. van Heel, David Chapman, David E. Douse 2002-06-04
6348827 Programmable delay element and synchronous DRAM using the same John A. Fifield, Nicholas M. van Heel, David Chapman, David E. Douse 2002-02-19