Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11868698 | Context-aware circuit design layout construct | Joshua David Tygert, Rwik Sengupta, Timothy H. Pylant | 2024-01-09 |
| 11803684 | Relative placement by application of layered abstractions | Joshua David Tygert | 2023-10-31 |
| 11354470 | System and method for device placement | Joshua David Tygert, Rwik Sengupta, Timothy H. Pylant | 2022-06-07 |
| 10796067 | EDA CAA with learning phase | Frank E. Gennari, Jeffrey E. Nelson, Jeffrey Lucas Russell, Ya-Chieh Lai, Jac Paul P. Condella | 2020-10-06 |
| 8341564 | Method and system for optimizing migrated implementation of a system design | — | 2012-12-25 |
| 7984399 | System and method for random defect yield simulation of chip with built-in redundancy | Roland Ruehl, Mathew Koshy, Udayan Gumaste | 2011-07-19 |
| 7613047 | Efficient circuit and method to measure resistance thresholds | John A. Gabric, Muthukumarasamy Karthikeyan, Jeffery H. Oppold | 2009-11-03 |
| 7495254 | Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices | Jerome B. Lasky | 2009-02-24 |
| 7194670 | Command multiplier for built-in-self-test | Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Toshiaki Kirihata, Alan D. Norris +2 more | 2007-03-20 |