Issued Patents All Time
Showing 25 most recent of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12080703 | Semiconductor cell blocks having non-integer multiple of cell heights | Vassilios Gerousis, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Reddy Palle +1 more | 2024-09-03 |
| 12046635 | VFET standard cell architecture with improved contact and super via | Jung-Ho Do | 2024-07-23 |
| 11868698 | Context-aware circuit design layout construct | Joshua David Tygert, Jonathan R. Fales, Timothy H. Pylant | 2024-01-09 |
| 11727258 | Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs | Borna J. Obradovic, Titash Rakshit, Joon Goo Hong, Ryan M. Hatcher, Jorge A. Kittl +1 more | 2023-08-15 |
| 11574111 | Electronic design tracing and tamper detection using automatically generated layout patterns | Jeffrey E. Nelson, Philippe Hurat, Jac Paul P. Condella | 2023-02-07 |
| 11552067 | Semiconductor cell blocks having non-integer multiple of cell heights | Vassilios Gerousis, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Reddy Palle +1 more | 2023-01-10 |
| 11461620 | Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs | Borna J. Obradovic, Titash Rakshit, Joon Goo Hong, Ryan M. Hatcher, Jorge A. Kittl +1 more | 2022-10-04 |
| 11354470 | System and method for device placement | Jonathan R. Fales, Joshua David Tygert, Timothy H. Pylant | 2022-06-07 |
| 11189692 | VFET standard cell architecture with improved contact and super via | Jung-Ho Do | 2021-11-30 |
| 11182686 | 4T4R ternary weight cell with high on/off ratio background | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Dharmendar Reddy Palle, Joon Goo Hong | 2021-11-23 |
| 11101320 | System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs) | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Dharmendar Reddy Palle, Joon Goo Hong | 2021-08-24 |
| 10985103 | Apparatus and method of forming backside buried conductor in integrated circuit | Joon Goo Hong | 2021-04-20 |
| 10916513 | Method and system for providing a reverse engineering resistant hardware embedded security module | Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Mark S. Rodder | 2021-02-09 |
| 10910313 | Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch | Mark S. Rodder, Joon Goo Hong, Titash Rakshit | 2021-02-02 |
| 10886224 | Power distribution network using buried power rail | Vassilios Gerousis, Joon Goo Hong, Kevin Traynor | 2021-01-05 |
| 10872662 | 2T2R binary weight cell with high on/off ratio background | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Dharmendar Reddy Palle, Joon Goo Hong | 2020-12-22 |
| 10868193 | Nanosheet field effect transistor cell architecture | Mark S. Rodder, Joon Goo Hong, Titash Rakshit | 2020-12-15 |
| 10861950 | Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch | Mark S. Rodder, Joon Goo Hong, Titash Rakshit | 2020-12-08 |
| 10832774 | Variation resistant 3T3R binary weight cell with low output current and high on/off ratio | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Dharmendar Reddy Palle, Joon Goo Hong | 2020-11-10 |
| 10811415 | Semiconductor device and method for making the same | Joon Goo Hong, Vassilios Gerousis, Mark S. Rodder | 2020-10-20 |
| 10784198 | Power rail for standard cell block | Andrew Paul Hoover, Matthew Berzins, Sam Tower, Mark S. Rodder | 2020-09-22 |
| 10566330 | Dielectric separation of partial GAA FETs | Mark S. Rodder, Borna J. Obradovic, Dharmendar Reddy Palle, Mohammad Ali Pourghaderi | 2020-02-18 |
| 10424581 | Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating | Titash Rakshit, Mark S. Rodder | 2019-09-24 |
| 10381315 | Method and system for providing a reverse-engineering resistant hardware embedded security module | Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Mark S. Rodder | 2019-08-13 |
| 10361195 | Semiconductor device with an isolation gate and method of forming | Mark S. Rodder | 2019-07-23 |