Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12080703 | Semiconductor cell blocks having non-integer multiple of cell heights | Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Reddy Palle +1 more | 2024-09-03 |
| 11605574 | Method of forming a thermal shield in a monolithic 3-d integrated circuit | Wei-E Wang, Mark S. Rodder | 2023-03-14 |
| 11552067 | Semiconductor cell blocks having non-integer multiple of cell heights | Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya, Dharmendar Reddy Palle +1 more | 2023-01-10 |
| 11189600 | Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding | Wei-E Wang, Mark S. Rodder | 2021-11-30 |
| 11158738 | Method of forming isolation dielectrics for stacked field effect transistors (FETs) | Wei-E Wang, Mark S. Rodder | 2021-10-26 |
| 10971420 | Method of forming a thermal shield in a monolithic 3-D integrated circuit | Wei-E Wang, Mark S. Rodder | 2021-04-06 |
| 10886224 | Power distribution network using buried power rail | Rwik Sengupta, Joon Goo Hong, Kevin Traynor | 2021-01-05 |
| 10811415 | Semiconductor device and method for making the same | Rwik Sengupta, Joon Goo Hong, Mark S. Rodder | 2020-10-20 |
| 10510774 | Integrated circuit power distribution network | Peter Debacker, Praveen Raghavan | 2019-12-17 |
| 10192018 | Method and system for implementing efficient trim data representation for an electronic design | Shane Zhang, Jianmin Li, Stefanus Mantik, Louis Tsai | 2019-01-29 |
| 9767245 | Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithography | Stefanus Mantik | 2017-09-19 |
| 9286432 | Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness | Shuo Zhang, Stefanus Mantik, Yuan Huang, Jing Chen, Jianmin Li | 2016-03-15 |
| 9245076 | Orthogonal circuit element routing | Lars Liebmann, Stefanus Mantik, Gustavo E. Tellez, Shuo Zhang | 2016-01-26 |
| 9087174 | Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs | Shuo Zhang | 2015-07-21 |
| 8863048 | Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design | Shuo Zhang, Stefanus Mantik, Yuan Huang, Jing Chen, Jianmin Li | 2014-10-14 |
| 8782570 | Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques | Jianmin Li, Jing Chen, Guowei ZHAO, Taufik Arifin, Yuan Huang +3 more | 2014-07-15 |
| 8782586 | Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning | Abdurrahman Sezginer, David C. Noice, Jason Sweis, Sozen Yao | 2014-07-15 |
| 8762908 | Static timing analysis with design-specific on chip variation de-rating factors | Hongliang Chang, Sireesha Molakalapalli, Sachin Shrivastava | 2014-06-24 |
| 8336010 | Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits | Hongliang Chang, Sireesha Molakalapalli, Sachin Shrivastava | 2012-12-18 |
| 8151229 | System and method of computing pin criticalities under process variations for timing analysis and optimization | Hongliang Chang, Oleg Levitsky, Nikolay Rubanov | 2012-04-03 |
| 8086978 | Method and system for performing statistical leakage characterization, analysis, and modeling | Lizheng Zhang, Parveen Khurana, Hongliang Chang, Sachin Shrivastava | 2011-12-27 |
| 8069432 | Method and system for performing statistical leakage characterization, analysis, and modeling | Lizheng Zhang, Hongliang Chang, Kai-Ti Huang | 2011-11-29 |