Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9760667 | Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs | Paul W. Kollaritsch | 2017-09-12 |
| 9165098 | Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Dinesh Gupta | 2015-10-20 |
| 9152742 | Multi-phase models for timing closure of integrated circuit designs | Dinesh Gupta | 2015-10-06 |
| 9141740 | Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data | Dongzi Liu | 2015-09-22 |
| 9053270 | Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs | Sushobhit Singh, Amit Kumar | 2015-06-09 |
| 8977995 | Timing budgeting of nested partitions for hierarchical integrated circuit designs | Sumit Arora, Amit Kumar, Sushobhit Singh | 2015-03-10 |
| 8977994 | Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints | Chien-Chu Kuo, Dinesh Gupta | 2015-03-10 |
| 8935642 | Methods for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Dinesh Gupta | 2015-01-13 |
| 8769455 | Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs | Sushobhit Singh, Amit Kumar | 2014-07-01 |
| 8745560 | Methods for generating a user interface for timing budget analysis of integrated circuit designs | Vivek Bhardwaj, Didier Seropian | 2014-06-03 |
| 8719743 | Method and system for implementing clock tree prototyping | Paul W. Kollaritsch, Lokeswara R. Korlipara | 2014-05-06 |
| 8640066 | Multi-phase models for timing closure of integrated circuit designs | Dinesh Gupta | 2014-01-28 |
| 8572532 | Common path pessimism removal for hierarchical timing analysis | Sushobhit Singh, Amit Kumar, Akash Khandelwal | 2013-10-29 |
| 8539402 | Systems for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Dinesh Gupta | 2013-09-17 |
| 8504978 | User interface for timing budget analysis of integrated circuit designs | Vivek Bhardwaj, Didier Seropian | 2013-08-06 |
| 8365113 | Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Dinesh Gupta | 2013-01-29 |
| 8151229 | System and method of computing pin criticalities under process variations for timing analysis and optimization | Hongliang Chang, Nikolay Rubanov, Vassilios Gerousis | 2012-04-03 |
| 7930675 | Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis | Kit Lam Cheong, Wilson Chan, Dongzi Liu | 2011-04-19 |
| 7926011 | System and method of generating hierarchical block-level timing constraints from chip-level timing constraints | Chien-Chu Kuo, Dinesh Gupta | 2011-04-12 |
| 6704697 | Unified timing analysis for model interface layout parasitics | Paul Berevoescu | 2004-03-09 |
| 6378113 | Black box transparency in a circuit timing model | Paul Berevoescu | 2002-04-23 |