Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332304 | System and method for automatic fault detection in an electronic design | Arvind Nembili Veeravalli, Naresh Kumar, Mahesh D. Sadhankar, Daksh Bakshi | 2025-06-17 |
| 11455450 | System and method for performing sign-off timing analysis of electronic circuit designs | Arvind Nembili Veeravalli, Naresh Kumar, Beenish, Mahesh D. Sadhankar, Ankit Sethi | 2022-09-27 |
| 11347915 | System and method for objective probing and generation of timing constraints associated with an electronic circuit design | Puneet Munjal, Naresh Kumar | 2022-05-31 |
| 10783300 | Systems and methods for extracting hierarchical path exception timing models | Naresh Kumar, Beenish, Ankur Gulati, Vishal Karda, Shashank Rajendra Prasad | 2020-09-22 |
| 10733346 | Systems and methods for arc-based debugging in an electronic design | — | 2020-08-04 |
| 9053270 | Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs | Amit Kumar, Oleg Levitsky | 2015-06-09 |
| 8977995 | Timing budgeting of nested partitions for hierarchical integrated circuit designs | Sumit Arora, Oleg Levitsky, Amit Kumar | 2015-03-10 |
| 8769455 | Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs | Amit Kumar, Oleg Levitsky | 2014-07-01 |
| 8572532 | Common path pessimism removal for hierarchical timing analysis | Amit Kumar, Oleg Levitsky, Akash Khandelwal | 2013-10-29 |