Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332304 | System and method for automatic fault detection in an electronic design | Sushobhit Singh, Naresh Kumar, Mahesh D. Sadhankar, Daksh Bakshi | 2025-06-17 |
| 11455450 | System and method for performing sign-off timing analysis of electronic circuit designs | Sushobhit Singh, Naresh Kumar, Beenish, Mahesh D. Sadhankar, Ankit Sethi | 2022-09-27 |
| 10114920 | Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic | Umesh Gupta, Shashank Tripathi, Naresh Kumar, Prashant Sethia, Ritika Govila | 2018-10-30 |
| 9881123 | Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact | Ratnakar Goyal, Manuj Verma, Igor Keller | 2018-01-30 |
| 8255850 | Fabricating IC with NBTI path delay within timing constraints | Palkesh Jain, Ajoy Mandal | 2012-08-28 |
| 8051399 | IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis | Ramamurthy Vishweshwara, Venkatraman Ramakrishnan, H Udayakumar | 2011-11-01 |