Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11023636 | Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window | Igor Keller, Ratnakar Goyal, Harmandeep Singh | 2021-06-01 |
| 10289774 | Systems and methods for reuse of delay calculation in static timing analysis | Pradeep Yadav, Ratnakar Goyal, Prashant Sethia | 2019-05-14 |
| 10031986 | System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based technique | Vishnu Kumar | 2018-07-24 |
| 9881123 | Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact | Ratnakar Goyal, Igor Keller, Arvind Nembili Veeravalli | 2018-01-30 |
| 9589096 | Method and apparatus for integrating spice-based timing using sign-off path-based analysis | Umesh Gupta, Vishnu Kumar, Manish Bansal, Naresh Kumar, Prashant Sethia | 2017-03-07 |
| 9529962 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Amit Dhuria, Pradeep Yadav, Naresh Kumar, Prashant Sethia | 2016-12-27 |
| 7464349 | Method and system or generating a current source model of a gate | Igor Keller | 2008-12-09 |