PS

Prashant Sethia

CS Cadence Design Systems: 11 patents #99 of 2,263Top 5%
Overall (All Time): #439,784 of 4,157,543Top 15%
11
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12423504 Adaptive path based analysis process Umesh Gupta, Marut Agarwal, Satyendra Patel, Naresh Kumar, Ankit Sethi +1 more 2025-09-23
10776547 Infinite-depth path-based analysis of operational timing for circuit design Umesh Gupta, Naresh Kumar, Ritika Govila, Jayant Sharma 2020-09-15
10289774 Systems and methods for reuse of delay calculation in static timing analysis Pradeep Yadav, Ratnakar Goyal, Manuj Verma 2019-05-14
10114920 Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic Umesh Gupta, Shashank Tripathi, Naresh Kumar, Arvind Nembili Veeravalli, Ritika Govila 2018-10-30
9875333 Comprehensive path based analysis process Sourabh Kumar Verma, Naresh Kumar, Ajay Tomar, Rakesh Agarwal, Umesh Gupta +2 more 2018-01-23
9633159 Method and system for performing distributed timing signoff and optimization Vipul Parikh, Lalit Bharat, Shagufta Siddique, Naresh Kumar 2017-04-25
9589096 Method and apparatus for integrating spice-based timing using sign-off path-based analysis Umesh Gupta, Vishnu Kumar, Manish Bansal, Naresh Kumar, Manuj Verma 2017-03-07
9529962 System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design Amit Dhuria, Pradeep Yadav, Manuj Verma, Naresh Kumar 2016-12-27
9405882 High performance static timing analysis system and method for input/output interfaces Amit Dhuria, Naresh Kumar, Jeannette Sutherland, Shashank Tripathi 2016-08-02
8863052 System and method for generating and using a structurally aware timing model for representative operation of a circuit design Amit Dhuria, Naresh Kumar, Umesh Gupta, Pradeep Yadav 2014-10-14
8788995 System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design Naresh Kumar, Amit Dhuria, Krishna Belkhale 2014-07-22