Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10915685 | Circuit stage credit based approaches to static timing analysis of integrated circuits | Umesh Gupta, Naresh Kumar, Rakesh Agarwal, Sukriti Khanna, Jayant Sharma | 2021-02-09 |
| 10776547 | Infinite-depth path-based analysis of operational timing for circuit design | Umesh Gupta, Naresh Kumar, Prashant Sethia, Jayant Sharma | 2020-09-15 |
| 10114920 | Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic | Umesh Gupta, Shashank Tripathi, Naresh Kumar, Arvind Nembili Veeravalli, Prashant Sethia | 2018-10-30 |