Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11256837 | Methods, systems, and computer program product for implementing an electronic design with high-capacity design closure | Sourav Kumar Sircar, Marc Heyberger, Manish Garg, Chunlong Pan, Ruchir Agarwal +5 more | 2022-02-22 |
| 10460059 | System and method for generating reduced standard delay format files for gate level simulation | Pawan Kulshreshtha, Rajarshi Mukherjee, Chih-kuo Yu | 2019-10-29 |
| 8572532 | Common path pessimism removal for hierarchical timing analysis | Sushobhit Singh, Amit Kumar, Oleg Levitsky | 2013-10-29 |