Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12321794 | Hybrid language model architecture for API orchestration including chain of thought | Giovanni Faonte, Shreya Chandrashekar Srinarasi, Mithun Azhagappan, Christopher M. Churchman, Cheska Adrianne Mauban | 2025-06-03 |
| 12242468 | Generative machine learning with retriever having reconfigurable sequence of rankers | Eliot Brenner, Koustuv Dasgupta, Manjunath G. Hegde, Amy Francesca Pajak, Goncalo Nuno Ventura de Melo +1 more | 2025-03-04 |
| 11968280 | Controlling ingestion of streaming data to serverless function executions | Vinayak Sood, Mandakini Saroop, Shu-Min Song, Tejas Mahadeo Ghadge, Tyson Charles Olychuck +1 more | 2024-04-23 |
| 11550505 | Intra-shard parallelization of data stream processing using virtual shards | Deepak Verma, Jiaxuan Lu | 2023-01-10 |
| 11388210 | Streaming analytics using a serverless compute system | Vinayak Sood, Jia Liu, Mandakini Saroop, Tejas Mahadeo Ghadge, Himanshu Sharma +3 more | 2022-07-12 |
| 9165098 | Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Oleg Levitsky | 2015-10-20 |
| 9152742 | Multi-phase models for timing closure of integrated circuit designs | Oleg Levitsky | 2015-10-06 |
| 8977994 | Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints | Oleg Levitsky, Chien-Chu Kuo | 2015-03-10 |
| 8935642 | Methods for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Oleg Levitsky | 2015-01-13 |
| 8640066 | Multi-phase models for timing closure of integrated circuit designs | Oleg Levitsky | 2014-01-28 |
| 8539402 | Systems for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Oleg Levitsky | 2013-09-17 |
| 8365113 | Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs | Vivek Bhardwaj, Oleg Levitsky | 2013-01-29 |
| 7926011 | System and method of generating hierarchical block-level timing constraints from chip-level timing constraints | Oleg Levitsky, Chien-Chu Kuo | 2011-04-12 |
| 7672315 | Methods and apparatus for deskewing VCAT/LCAS members | Dev Shankar Mukherjee, Rakesh Malik | 2010-03-02 |
| 7558287 | Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) | Rakesh Malik, Dev Shankar Mukherjee, Harsh Chilwal | 2009-07-07 |