Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12235836 | Representing listings for reservations on map | Adam James Shutsa, Ang Li, Clarence Chin-wei Quah, Devansh Gupta, Shuoyuan Lin +10 more | 2025-02-25 |
| 9165098 | Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs | Oleg Levitsky, Dinesh Gupta | 2015-10-20 |
| 8935642 | Methods for single pass parallel hierarchical timing closure of integrated circuit designs | Oleg Levitsky, Dinesh Gupta | 2015-01-13 |
| 8745560 | Methods for generating a user interface for timing budget analysis of integrated circuit designs | Didier Seropian, Oleg Levitsky | 2014-06-03 |
| 8539402 | Systems for single pass parallel hierarchical timing closure of integrated circuit designs | Oleg Levitsky, Dinesh Gupta | 2013-09-17 |
| 8504978 | User interface for timing budget analysis of integrated circuit designs | Didier Seropian, Oleg Levitsky | 2013-08-06 |
| 8365113 | Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs | Oleg Levitsky, Dinesh Gupta | 2013-01-29 |