DS

Didier Seropian

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Overall (All Time): #2,051,852 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8745560 Methods for generating a user interface for timing budget analysis of integrated circuit designs Vivek Bhardwaj, Oleg Levitsky 2014-06-03
8504978 User interface for timing budget analysis of integrated circuit designs Vivek Bhardwaj, Oleg Levitsky 2013-08-06