Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8977994 | Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints | Oleg Levitsky, Dinesh Gupta | 2015-03-10 |
| 7926011 | System and method of generating hierarchical block-level timing constraints from chip-level timing constraints | Oleg Levitsky, Dinesh Gupta | 2011-04-12 |
| 7467367 | Method and system for clock tree synthesis of an integrated circuit | Hung-Chun Li, Minghorng Lai, Ming-Chyuan Chen | 2008-12-16 |