HC

Hongliang Chang

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
IBM: 2 patents #32,839 of 70,183Top 50%
📍 Windom, MN: #481 of 2,819 inventorsTop 20%
🗺 Minnesota: #10,397 of 52,454 inventorsTop 20%
Overall (All Time): #741,590 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
8762908 Static timing analysis with design-specific on chip variation de-rating factors Vassilios Gerousis, Sireesha Molakalapalli, Sachin Shrivastava 2014-06-24
8336010 Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits Vassilios Gerousis, Sireesha Molakalapalli, Sachin Shrivastava 2012-12-18
8151229 System and method of computing pin criticalities under process variations for timing analysis and optimization Oleg Levitsky, Nikolay Rubanov, Vassilios Gerousis 2012-04-03
8086978 Method and system for performing statistical leakage characterization, analysis, and modeling Lizheng Zhang, Parveen Khurana, Vassilios Gerousis, Sachin Shrivastava 2011-12-27
8069432 Method and system for performing statistical leakage characterization, analysis, and modeling Lizheng Zhang, Kai-Ti Huang, Vassilios Gerousis 2011-11-29
8015525 System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis Sambasivan Narayan, Chandramouli Visweswariah, Vladimir Zolotov 2011-09-06
7293248 System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis Sambasivan Narayan, Chandramouli Visweswariah, Vladimir Zolotov 2007-11-06