SM

Sireesha Molakalapalli

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 San Jose, CA: #17,604 of 32,062 inventorsTop 55%
🗺 California: #185,134 of 386,348 inventorsTop 50%
Overall (All Time): #2,053,129 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8762908 Static timing analysis with design-specific on chip variation de-rating factors Hongliang Chang, Vassilios Gerousis, Sachin Shrivastava 2014-06-24
8336010 Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits Hongliang Chang, Vassilios Gerousis, Sachin Shrivastava 2012-12-18