Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9652582 | Multi-instantiated block timing optimization | Pinhong Chen, Deng Pan | 2017-05-16 |
| 9639644 | Method and apparatus for master-clone optimization during circuit analysis | Deng Pan | 2017-05-02 |
| 9141740 | Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data | Oleg Levitsky | 2015-09-22 |
| 9026978 | Reverse interface logic model for optimizing physical hierarchy under full chip constraint | Yi Qian, Wanshuan Liu, Pinhong Chen, WenHsing Tsai, Yanhui Wang | 2015-05-05 |
| 7930675 | Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis | Oleg Levitsky, Kit Lam Cheong, Wilson Chan | 2011-04-19 |