WL

Wanshuan Liu

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #3,051,425 of 4,157,543Top 75%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9026978 Reverse interface logic model for optimizing physical hierarchy under full chip constraint Dongzi Liu, Yi Qian, Pinhong Chen, WenHsing Tsai, Yanhui Wang 2015-05-05