SM

Stefanus Mantik

CS Cadence Design Systems: 6 patents #235 of 2,263Top 15%
IBM: 1 patents #44,794 of 70,183Top 65%
Overall (All Time): #702,888 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
11615229 Pattern-based formal description language for describing a power/ground routing structure in an integrated circuit design Jianmin Li, Dennis Huang, Dewi Farrah Santoso, Ting Li, Ming Zhang 2023-03-28
10192018 Method and system for implementing efficient trim data representation for an electronic design Vassilios Gerousis, Shane Zhang, Jianmin Li, Louis Tsai 2019-01-29
9767245 Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithography Vassilios Gerousis 2017-09-19
9286432 Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness Vassilios Gerousis, Shuo Zhang, Yuan Huang, Jing Chen, Jianmin Li 2016-03-15
9245076 Orthogonal circuit element routing Vassilios Gerousis, Lars Liebmann, Gustavo E. Tellez, Shuo Zhang 2016-01-26
8863048 Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design Vassilios Gerousis, Shuo Zhang, Yuan Huang, Jing Chen, Jianmin Li 2014-10-14
7594207 Computationally efficient design rule checking for circuit interconnect routing design Limin He, Soohong Kim, Jimmy Lam, Jianmin Li 2009-09-22