Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12080703 | Semiconductor cell blocks having non-integer multiple of cell heights | Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya +1 more | 2024-09-03 |
| 11556768 | Optimization of sparsified neural network layers for semi-digital crossbar architectures | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Joon Goo Hong | 2023-01-17 |
| 11552067 | Semiconductor cell blocks having non-integer multiple of cell heights | Vassilios Gerousis, Rwik Sengupta, Joon Goo Hong, Kevin Traynor, Tanya Abaya +1 more | 2023-01-10 |
| 11475933 | Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Joon Goo Hong | 2022-10-18 |
| 11217392 | Composite piezoelectric capacitor | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Joon Goo Hong | 2022-01-04 |
| 11182686 | 4T4R ternary weight cell with high on/off ratio background | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Rwik Sengupta, Joon Goo Hong | 2021-11-23 |
| 11101320 | System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs) | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Rwik Sengupta, Joon Goo Hong | 2021-08-24 |
| 10872662 | 2T2R binary weight cell with high on/off ratio background | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Rwik Sengupta, Joon Goo Hong | 2020-12-22 |
| 10832774 | Variation resistant 3T3R binary weight cell with low output current and high on/off ratio | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Rwik Sengupta, Joon Goo Hong | 2020-11-10 |
| 10566330 | Dielectric separation of partial GAA FETs | Mark S. Rodder, Borna J. Obradovic, Rwik Sengupta, Mohammad Ali Pourghaderi | 2020-02-18 |
| 10205025 | Methods to achieve strained channel finFET devices | Jorge A. Kittl, Joon Goo Hong, Mark S. Rodder | 2019-02-12 |
| 10181527 | FinFet having dual vertical spacer and method of manufacturing the same | Borna J. Obradovic, Joon Goo Hong, Mark S. Rodder | 2019-01-15 |
| 9978833 | Methods for varied strain on nano-scale field effect transistor devices | Jorge A. Kittl, Joon Goo Hong, Mark S. Rodder | 2018-05-22 |
| 9905672 | Method of forming internal dielectric spacers for horizontal nanosheet FET architectures | Wei-E Wang, Mark S. Rodder, Borna J. Obradovic, Joon Goo Hong | 2018-02-27 |
| 9871139 | Sacrificial epitaxial gate stressors | Jorge A. Kittl, Joon Goo Hong, Mark S. Rodder | 2018-01-16 |
| 9773886 | Nanosheet and nanowire devices having doped internal spacers and methods of manufacturing the same | Jorge A. Kittl, Mark S. Rodder | 2017-09-26 |
| 9647098 | Thermionically-overdriven tunnel FETs and methods of fabricating the same | Borna J. Obradovic, Robert C. Bowen, Mark S. Rodder | 2017-05-09 |
| 9431492 | Integrated circuit devices including contacts and methods of forming the same | Jorge A. Kittl, Mark S. Rodder | 2016-08-30 |
| 9425275 | Integrated circuit chips having field effect transistors with different gate designs | Mark S. Rodder, Borna J. Obradovic | 2016-08-23 |
| 9287357 | Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same | Mark S. Rodder, Borna J. Obradovic, Rwik Sengupta, Robert C. Bowen | 2016-03-15 |
| 8263967 | Bi-layer pseudo-spin field-effect transistor | Sanjay Banerjee, Leonard Franklin Register, II, Allan MacDonald, Emanuel Tutuc | 2012-09-11 |
| 8188460 | Bi-layer pseudo-spin field-effect transistor | Sanjay Banerjee, Leonard Franklin Register, II, Allan MacDonald, Emanuel Tutuc | 2012-05-29 |