Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11574111 | Electronic design tracing and tamper detection using automatically generated layout patterns | Rwik Sengupta, Jeffrey E. Nelson, Jac Paul P. Condella | 2023-02-07 |
| 8255840 | Silicon tolerance specification using shapes as design intent markers | Michel Cote, Michael L. Rieger, Robert M. Lugg, Jeff Mayhew | 2012-08-28 |
| 7458045 | Silicon tolerance specification using shapes as design intent markers | Michel Cote, Michael L. Rieger, Robert M. Lugg, Jeff Mayhew | 2008-11-25 |
| 6807663 | Accelerated layout processing using OPC pre-processing | Michel Cote, Christophe Pierrat | 2004-10-19 |
| 6745372 | Method and apparatus for facilitating process-compliant layout optimization | Michel Cote, Christophe Pierrat | 2004-06-01 |