JT

Joshua David Tygert

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 Seneca, PA: #23 of 55 inventorsTop 45%
🗺 Pennsylvania: #23,606 of 74,527 inventorsTop 35%
Overall (All Time): #1,350,394 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11868698 Context-aware circuit design layout construct Jonathan R. Fales, Rwik Sengupta, Timothy H. Pylant 2024-01-09
11803684 Relative placement by application of layered abstractions Jonathan R. Fales 2023-10-31
11354470 System and method for device placement Jonathan R. Fales, Rwik Sengupta, Timothy H. Pylant 2022-06-07