Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11092649 | Method for reducing power consumption in scannable flip-flops without additional circuitry | — | 2021-08-17 |
| 10819342 | Low-power low-setup integrated clock gating cell with complex enable selection | Lalitkumar Motagi | 2020-10-27 |
| 10784198 | Power rail for standard cell block | Rwik Sengupta, Andrew Paul Hoover, Sam Tower, Mark S. Rodder | 2020-09-22 |
| 10784864 | Low power integrated clock gating system and method | Lalitkumar Motagi, Shyam Agarwal | 2020-09-22 |
| 10748889 | Power grid and standard cell co-design structure and methods thereof | Andrew Paul Hoover, Christopher Alan Peura | 2020-08-18 |
| 10720204 | System and method for improving scan hold-time violation and low voltage operation in sequential circuit | — | 2020-07-21 |
| 10607982 | Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell | Charles A. Cornell | 2020-03-31 |
| 10581410 | High speed domino-based flip flop | James Jung Lim | 2020-03-03 |
| 10382017 | Dynamic flip flop having data independent P-stack feedback | Sumanth Suraneni | 2019-08-13 |
| 10353000 | Multi-bit flip-flops | Doo-seok YOON, Min Su Kim, Chung-Hee Kim, Dae Seong Lee, Hyun Seok Lee +1 more | 2019-07-16 |
| 10298235 | Low power integrated clock gating cell using controlled inverted clock | James Jung Lim | 2019-05-21 |
| 10262723 | System and method for improving scan hold-time violation and low voltage operation in sequential circuit | — | 2019-04-16 |
| 9904758 | Using deep sub-micron stress effects and proximity effects to create a high performance standard cell | Andrew Paul Hoover | 2018-02-27 |
| 9899990 | Semiconductor circuit including flip-flop | San Ha Kim, Min Su Kim | 2018-02-20 |
| 9891283 | Multi-bit flip-flops and scan chain circuits | Min Su Kim, Jong Woo Kim | 2018-02-13 |
| 9793881 | Flip-flop with zero-delay bypass mux | Christina Wells, Min Su Kim | 2017-10-17 |
| 9779201 | Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design | Brian Millar, Ahsan Chowdhury, Suhail Ahmed, Jinkyu Lee | 2017-10-03 |
| 9768756 | Low power integrated clock gating cell with internal control signal | James Jung Lim | 2017-09-19 |
| 9564897 | Apparatus for low power high speed integrated clock gating cell | James Jung Lim | 2017-02-07 |
| 9473117 | Multi-bit flip-flops and scan chain circuits | Min Su Kim, Jong Woo Kim | 2016-10-18 |
| 9450578 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Prashant U. Kenkare | 2016-09-20 |
| 9419590 | Low power toggle latch-based flip-flop including integrated clock gating logic | Christina Wells | 2016-08-16 |
| 9203382 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Prashant U. Kenkare | 2015-12-01 |
| 8975949 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Prashant U. Kenkare | 2015-03-10 |
| 8289060 | Pulsed state retention power gating flip-flop | Samuel J. Tower, Charles A. Cornell | 2012-10-16 |