Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11271011 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Abhishek Ghosh, Parvinder Kumar Rana | 2022-03-08 |
| 10784864 | Low power integrated clock gating system and method | Matthew Berzins, Lalitkumar Motagi | 2020-09-22 |
| 10748932 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Abhishek Ghosh, Parvinder Kumar Rana | 2020-08-18 |
| 10715118 | Flip-flop with single pre-charge node | Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Ghosh, Parvinder Kumar Rana | 2020-07-14 |
| 10103172 | Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE) | Abhishek Ghosh, Parvinder Kumar Rana | 2018-10-16 |
| 6605569 | Mg-doped high-temperature superconductor having low superconducting anisotropy and method for producing the superconductor | Hideo Ihara | 2003-08-12 |
| 6281171 | MG-doped high-temperature superconductor having the superconducting anisotropy and method for producing the superconductor | Hideo Ihara | 2001-08-28 |