Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11790982 | Circuits for power down leakage reduction in random-access memory | Ankur Gupta, Manish Chandra Joshi | 2023-10-17 |
| 11776623 | Bitline precharge system for a semiconductor memory device | Lava Kumar Pulluru, Ankur Gupta | 2023-10-03 |
| 11410720 | Bitline precharge system for a semiconductor memory device | Lava Kumar Pulluru, Ankur Gupta | 2022-08-09 |
| 11290092 | Level shifter circuits | Ankur Gupta, Lava Kumar Pulluru | 2022-03-29 |
| 11271011 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Shyam Agarwal, Abhishek Ghosh | 2022-03-08 |
| 11017848 | Static random-access memory (SRAM) system with delay tuning and control and a method thereof | Ambuj Jain, Akash GUPTA, Manish Chandra Joshi, Abhishek Kesarwani | 2021-05-25 |
| 10998018 | Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory | Shubham RANJAN, Janardhan Achanta, Manish Chandra Joshi | 2021-05-04 |
| 10803929 | Static random-access memory with virtual banking architecture, and system and method including the same | Lava Kumar Pulluru, Akash GUPTA, Gayatri Nair | 2020-10-13 |
| 10748932 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Shyam Agarwal, Abhishek Ghosh | 2020-08-18 |
| 10715118 | Flip-flop with single pre-charge node | Shyam Agarwal, Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Ghosh | 2020-07-14 |
| 10672443 | Methods and systems for performing decoding in finFET based memories | Ankur Gupta, Abhishek Kesarwani, Manish Chandra Joshi, Lava Kumar Pulluru | 2020-06-02 |
| 10665295 | Static random-access memory with virtual banking architecture, and system and method including the same | Lava Kumar Pulluru, Akash GUPTA, Gayatri Nair | 2020-05-26 |
| 10651850 | Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library | Sajal Mittal, Jaskaran Singh Bhatia, Rajeela Deshpande, Nikhila C M, Abhishek Ghosh +1 more | 2020-05-12 |
| 10566959 | Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit | Sajal Mittal, Abhishek Ghosh, Rajeela Deshpande | 2020-02-18 |
| 10522218 | Methods and apparatuses to reduce power dissipation in a static random access memory (SRAM) device | Lava Kumar Pulluru, Shuvadeep Kumar, Ankur Gupta | 2019-12-31 |
| 10304507 | Memory providing signal buffering scheme for array and periphery signals and operating method of the same | Manish Chandra Joshi, Akash GUPTA | 2019-05-28 |
| 10147493 | System on-chip (SoC) device with dedicated clock generator for memory banks | Lava Kumar Pulluru, Manish Chandra Joshi | 2018-12-04 |
| 10103172 | Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE) | Shyam Agarwal, Abhishek Ghosh | 2018-10-16 |
| 9576621 | Read-current and word line delay path tracking for sense amplifier enable timing | Anand Seshadri, Dharin N. Shah, Wah Kit Loh | 2017-02-21 |
| 9496024 | Automatic latch-up prevention in SRAM | Srinivasa Raghavan Sridhara, Sanjeev Kumar Suman, Premkumar Seetharaman, Keshav Bhaktavatson Chintamani, Atul Ramakant Lele +5 more | 2016-11-15 |
| 9001570 | Pseudo retention till access mode enabled memory | Rashmi Sachan, Abhishek Kesarwani, Robert L. Pitts | 2015-04-07 |
| 8958254 | High performance two-port SRAM architecture using 8T high performance single port bit cell | Manish Chandra Joshi, Lakshmikantha V. Holla | 2015-02-17 |
| 8284626 | Voltage compensated tracking circuit in SRAM | Ravi Prasad | 2012-10-09 |
| 8228749 | Margin testing of static random access memory cells | Xiaowei Deng, Wah Kit Loh, Lakshmikantha V. Holla | 2012-07-24 |
| 8120439 | Fast start-up crystal oscillator | Aatmesh Shrivastava, Rajesh Yadav | 2012-02-21 |