Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020774 | Methods and systems for selectively enabling/disabling memory dies | Sneha Bhatia, Venkatesh Ramachandra, Anil Pai | 2024-06-25 |
| 11935622 | Free flow data path architectures | Sneha Bhatia | 2024-03-19 |
| 11152942 | Three-input exclusive NOR/OR gate using a CMOS circuit | Hareharan Nagarajan, Abhishek Ghosh | 2021-10-19 |
| 11048443 | Non-volatile memory interface | Sneha Bhatia, Vinayak Ghatawade | 2021-06-29 |
| 11050424 | Current-mirror based level shifter circuit and methods for implementing the same | Hareharan Nagarajan, Abdur Rakheeb, Nandish Uppal Raravi, Vinod Sharma | 2021-06-29 |
| 10817223 | Unified chip enable, address and command latch enable protocol for nand memory | Sneha Bhatia, Vinayak Ghatawade | 2020-10-27 |
| 10812055 | Flip flop circuit | Aroma Bhat, Hareharan Nagarajan, Rahul Kataria, Abhishek Ghosh | 2020-10-20 |
| 10672756 | Area and power efficient circuits for high-density standard cell libraries | Abhishek Ghosh, Utkarsh GARG | 2020-06-02 |
| 10651850 | Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library | Jaskaran Singh Bhatia, Rajeela Deshpande, Parvinder Kumar Rana, Nikhila C M, Abhishek Ghosh +1 more | 2020-05-12 |
| 10566959 | Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit | Parvinder Kumar Rana, Abhishek Ghosh, Rajeela Deshpande | 2020-02-18 |