Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10446201 | Distributed global-bitline keeper/precharge/header circuit for low voltage operation | Sumeer Goel | 2019-10-15 |
| 10003325 | System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits | Sumeer Goel, Kenneth Hicks, Jan-Michael Huber, Rajesh Kapaluru | 2018-06-19 |
| 9697889 | Method and apparatus for read assist to achieve robust static random access memory (SRAM) | Kevin Klein | 2017-07-04 |
| 9647453 | Dual supply memory | Brian Millar, Frank Philip Helms | 2017-05-09 |
| 9460778 | Static random access memory with bitline boost | Jin Seung Son | 2016-10-04 |
| 9450578 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Matthew Berzins | 2016-09-20 |
| 9337840 | Voltage level shifter and systems implementing the same | Jin Seung Son | 2016-05-10 |
| 9330751 | SRAM wordline driver supply block with multiple modes | Shahnaz Nagle | 2016-05-03 |
| 9312857 | Semiconductor circuit | Min Su Kim, Jin Seung Son | 2016-04-12 |
| 9203382 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Matthew Berzins | 2015-12-01 |
| 9059687 | Flip-flop having shared feedback and method of operation | Ravindraraj Ramaraju | 2015-06-16 |
| 9021194 | Memory management unit tag memory | Ravindraraj Ramaraju, David R. Bearden, Jogendra C. Sarker | 2015-04-28 |
| 8975949 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Matthew Berzins | 2015-03-10 |
| 8943292 | System and method for memory array access with fast address decoder | Ravindraraj Ramaraju, David R. Bearden | 2015-01-27 |
| 8791739 | Flip-flop having shared feedback and method of operation | Ravindraraj Ramaraju | 2014-07-29 |
| 8634263 | Integrated circuit having memory repair information storage and method therefor | Troy L. Cooper, Andrew C. Russell, Shayan Zhang | 2014-01-21 |
| 8484523 | Sequential digital circuitry with test scan | Ravindraraj Ramaraju, Gary A. Mussemann, Mihir S. Sabnis | 2013-07-09 |
| 8315117 | Integrated circuit memory having assisted access and method therefor | Shayan Zhang, Troy L. Cooper, Jack M. Higman, Andrew C. Russell | 2012-11-20 |
| 8156357 | Voltage-based memory size scaling in a data processing system | Shayan Zhang, James D. Burnett, Hema Ramamurthy, Andrew C. Russell, Michael D. Snyder | 2012-04-10 |
| 8143929 | Flip-flop having shared feedback and method of operation | Ravindraraj Ramaraju | 2012-03-27 |
| 8120975 | Memory having negative voltage write assist circuit and method therefor | Troy L. Cooper | 2012-02-21 |
| 8059482 | Memory using multiple supply voltages | Andrew C. Russell, Shayan Zhang | 2011-11-15 |
| 8031549 | Integrated circuit having boosted array voltage and method therefor | Troy L. Cooper | 2011-10-04 |
| 8009489 | Memory with read cycle write back | Shayan Zhang, Jack M. Higman, Pelley H. Perry, Andrew C. Russell | 2011-08-30 |
| 8004907 | SRAM with read and write assist | Andrew C. Russell, Troy L. Cooper, Shayan Zhang | 2011-08-23 |