Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12299447 | Hardware verification of dynamically generated code | Jeffrey E. Gonion, Filip J. Pizlo | 2025-05-13 |
| 11893413 | Virtual channel support using write table | Ronald P. Hall, Deepak Limaye, Brett S. Feero, Rohit Gupta | 2024-02-06 |
| 11816484 | Hardware verification of dynamically generated code | Jeffrey E. Gonion, Filip J. Pizlo | 2023-11-14 |
| 9395983 | Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation | William C. Moyer, Gary L. Whisenhunt | 2016-07-19 |
| 9213665 | Data processor for processing a decorated storage notify | William C. Moyer, Gary L. Whisenhunt | 2015-12-15 |
| 9047079 | Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition | Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May +2 more | 2015-06-02 |
| 9026742 | System and method for processing potentially self-inconsistent memory transactions | Sanjay Deshpande, Klas Magnus Bruce | 2015-05-05 |
| 8990633 | Tracing support for interconnect fabric | Zheng Xu, Sanjay Deshpande | 2015-03-24 |
| 8972671 | Method and apparatus for cache transactions in a data processing system | William C. Moyer | 2015-03-03 |
| 8832702 | Thread de-emphasis instruction for multithreaded processor | Klas Magnus Bruce, Sergio Schuler, Matt B. Smittle, Gary L. Whisenhunt | 2014-09-09 |
| 8627471 | Permissions checking for data processing instructions | William C. Moyer, Gary L. Whisenhunt | 2014-01-07 |
| 8615644 | Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition | Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May +2 more | 2013-12-24 |
| 8539485 | Polling using reservation mechanism | Gary L. Whisenhunt | 2013-09-17 |
| 8531899 | Methods for testing a memory embedded in an integrated circuit | Shayan Zhang, James D. Burnett, Kent P. Fancher, Andrew C. Russell | 2013-09-10 |
| 8380779 | Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand | Klas Magnus Bruce, Ravindraraj Ramaraju, David R. Bearden | 2013-02-19 |
| 8379466 | Integrated circuit having an embedded memory and method for testing the memory | Shayan Zhang, James D. Burnett, Kent P. Fancher, Andrew C. Russell | 2013-02-19 |
| 8261047 | Qualification of conditional debug instructions based on address | William C. Moyer, Gary L. Whisenhunt | 2012-09-04 |
| 8199547 | Error detection in a content addressable memory (CAM) | Ravindraraj Ramaraju | 2012-06-12 |
| 8156357 | Voltage-based memory size scaling in a data processing system | Shayan Zhang, James D. Burnett, Prashant U. Kenkare, Hema Ramamurthy, Andrew C. Russell | 2012-04-10 |
| 8122437 | Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors | Zheng Xu, Suraj Bhaskaran, Klas Magnus Bruce, Jason T. Nearing, Paul B. Rawlins +1 more | 2012-02-21 |
| 8117618 | Forward progress mechanism for a multithreaded processor | David C. Holloway, Trinh Huy Nguyen, Gary L. Whisenhunt | 2012-02-14 |
| 8041901 | Performance monitoring device and method thereof | — | 2011-10-18 |
| 7941646 | Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor | David C. Holloway, Suresh K. Venkumahanti | 2011-05-10 |
| 7941499 | Interprocessor message transmission via coherency-based interconnect | Becky Bruce, Sanjay Deshpande, Gary L. Whisenhunt, Kumar K. Gala | 2011-05-10 |
| 7852692 | Memory operation testing | Shayan Zhang, Jack M. Higman | 2010-12-14 |