Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9442870 | Interrupt priority management using partition-based priority blocking processor registers | Bryan D. Marietta, Kumar K. Gala, David B. Kramer | 2016-09-13 |
| 9436626 | Processor interrupt interface with interrupt partitioning and virtualization enhancements | Bryan D. Marietta, Kumar K. Gala, David B. Kramer | 2016-09-06 |
| 9395983 | Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation | William C. Moyer, Michael D. Snyder | 2016-07-19 |
| 9229884 | Virtualized instruction extensions for system partitioning | Bryan D. Marietta, Kumar K. Gala, David B. Kramer | 2016-01-05 |
| 9213665 | Data processor for processing a decorated storage notify | William C. Moyer, Michael D. Snyder | 2015-12-15 |
| 9152587 | Virtualized interrupt delay mechanism | Bryan D. Marietta, Kumar K. Gala, David B. Kramer | 2015-10-06 |
| 9047079 | Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition | Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May +2 more | 2015-06-02 |
| 8832702 | Thread de-emphasis instruction for multithreaded processor | Klas Magnus Bruce, Sergio Schuler, Matt B. Smittle, Michael D. Snyder | 2014-09-09 |
| 8627471 | Permissions checking for data processing instructions | William C. Moyer, Michael D. Snyder | 2014-01-07 |
| 8615644 | Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition | Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May +2 more | 2013-12-24 |
| 8539485 | Polling using reservation mechanism | Michael D. Snyder | 2013-09-17 |
| 8261047 | Qualification of conditional debug instructions based on address | William C. Moyer, Michael D. Snyder | 2012-09-04 |
| 8117618 | Forward progress mechanism for a multithreaded processor | David C. Holloway, Trinh Huy Nguyen, Michael D. Snyder | 2012-02-14 |
| 8095831 | Programmable error actions for a cache in a data processing system | William C. Moyer | 2012-01-10 |
| 7941499 | Interprocessor message transmission via coherency-based interconnect | Becky Bruce, Sanjay Deshpande, Michael D. Snyder, Kumar K. Gala | 2011-05-10 |
| 7849247 | Interrupt controller for accelerated interrupt handling in a data processing system and method thereof | Bryan D. Marietta, Michael D. Snyder, Daniel L. Bouvier | 2010-12-07 |
| 7827360 | Cache locking device and methods thereof | Syed R. Rahman, David F. Greenberg, Kathryn C. Stacer, Klas Magnus Bruce, Matt B. Smittle +1 more | 2010-11-02 |
| 7805581 | Multiple address and arithmetic bit-mode data processing device and methods thereof | Michael D. Snyder, David C. Holloway, Trinh Huy Nguyen, Sergio Schuler | 2010-09-28 |
| 7702881 | Method and system for data transfers across different address spaces | Becky Bruce, Michael D. Snyder, Kumar K. Gala | 2010-04-20 |
| 7689815 | Debug instruction for use in a data processing system | William C. Moyer, Michael D. Snyder | 2010-03-30 |
| 7584344 | Instruction for conditionally yielding to a ready thread based on priority criteria | William C. Moyer | 2009-09-01 |
| 6792502 | Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation | Mihir Pandya | 2004-09-14 |
| 6145122 | Development interface for a data processor | Gary Lynn Miller, David R. Gonzales | 2000-11-07 |