Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12013807 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2024-06-18 |
| 12014214 | Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture | Malav Parikh, Vimal Reddy, Zainab Nasreen Zaidi, Paul Toth, Adam Caughron +6 more | 2024-06-18 |
| 11915005 | Branch predictor triggering | Chang Joo Lee, Michael Brian SCHINZLER, Yasuo Ishii | 2024-02-27 |
| 11475973 | Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture | Malav Parikh, Zainab Nasreen Zaidi, Natarajan Seshan, Raul A. Garibay, Jr., David Fick | 2022-10-18 |
| 11360932 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2022-06-14 |
| 11049586 | Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture | Malav Parikh, Zainab Nasreen Zaidi, Natarajan Seshan, Raul A. Garibay, Jr., David Fick | 2021-06-29 |
| 11016810 | Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture | Malav Parikh, Vimal Reddy, Zainab Nasreen Zaidi, Paul Toth, Adam Caughron +6 more | 2021-05-25 |
| 10891084 | Apparatus and method for providing data to a master device | Alex James Waugh, Geoffray Mattheiu Lacourba, Andrew John Turner | 2021-01-12 |
| 10606797 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2020-03-31 |
| 10521395 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2019-12-31 |
| 8832702 | Thread de-emphasis instruction for multithreaded processor | Klas Magnus Bruce, Matt B. Smittle, Michael D. Snyder, Gary L. Whisenhunt | 2014-09-09 |
| 7805581 | Multiple address and arithmetic bit-mode data processing device and methods thereof | Michael D. Snyder, David C. Holloway, Trinh Huy Nguyen, Gary L. Whisenhunt | 2010-09-28 |
| 7681021 | Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch | Michael D. Snyder, Leick D. Robinson, David Matthew Thompson | 2010-03-16 |