Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12014214 | Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture | Malav Parikh, Sergio Schuler, Vimal Reddy, Paul Toth, Adam Caughron +6 more | 2024-06-18 |
| 12013807 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2024-06-18 |
| 11475973 | Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture | Malav Parikh, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, Jr., David Fick | 2022-10-18 |
| 11360932 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2022-06-14 |
| 11049586 | Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture | Malav Parikh, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, Jr., David Fick | 2021-06-29 |
| 11016810 | Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture | Malav Parikh, Sergio Schuler, Vimal Reddy, Paul Toth, Adam Caughron +6 more | 2021-05-25 |
| 10606797 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2020-03-31 |
| 10521395 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2019-12-31 |
| 10114729 | Performance analysis using performance counters and trace logic | Sean T. Baartmans | 2018-10-30 |