Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12014214 | Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture | Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Nasreen Zaidi, Paul Toth +6 more | 2024-06-18 |
| 12013807 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2024-06-18 |
| 11475973 | Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture | Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, David Fick | 2022-10-18 |
| 11360932 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2022-06-14 |
| 11049586 | Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture | Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, David Fick | 2021-06-29 |
| 11016810 | Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture | Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Nasreen Zaidi, Paul Toth +6 more | 2021-05-25 |
| 10719651 | Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocks | Manadher Kharroubi | 2020-07-21 |
| 10606797 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2020-03-31 |
| 10521395 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2019-12-31 |
| 7900076 | Power management method for a pipelined computer system | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2011-03-01 |
| 7900075 | Pipelined computer system with power management control | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2011-03-01 |
| 7509512 | Instruction-initiated method for suspending operation of a pipelined data processor | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2009-03-24 |
| 7237065 | Configurable cache system depending on instruction type | Thang M. Tran, Muralidharan S. Chinnakonda, Paul K. Miller | 2007-06-26 |
| 7120810 | Instruction-initiated power management method for a pipelined data processor | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2006-10-10 |
| 7085978 | Validating test signal connections within an integrated circuit | Teresa Louise McLaurin, Peter Logan Harrod | 2006-08-01 |
| 7062666 | Signal-initiated method for suspending operation of a pipelined data processor | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2006-06-13 |
| 7000132 | Signal-initiated power management method for a pipelined data processor | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2006-02-14 |
| 6978390 | Pipelined data processor with instruction-initiated power management control | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2005-12-20 |
| 6910141 | Pipelined data processor with signal-initiated power management control | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2005-06-21 |
| 6721894 | METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2004-04-13 |
| 6694443 | SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2004-02-17 |
| 6343363 | Method of invoking a low power mode in a computer system using a halt instruction | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2002-01-29 |
| 6219773 | System and method of retiring misaligned write operands from a write buffer | Marc A. Quattromani | 2001-04-17 |
| 6138230 | Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline | Mark W. Hervin, Steven C. McMahan, Mark Bluhm | 2000-10-24 |
| 6088807 | Computer system with low power mode invoked by halt instruction | Robert Maher, Margaret R. Herubin, Mark Bluhm | 2000-07-11 |