Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7900075 | Pipelined computer system with power management control | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2011-03-01 |
| 7900076 | Power management method for a pipelined computer system | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2011-03-01 |
| 7509512 | Instruction-initiated method for suspending operation of a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2009-03-24 |
| 7120810 | Instruction-initiated power management method for a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2006-10-10 |
| 7062666 | Signal-initiated method for suspending operation of a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2006-06-13 |
| 7000132 | Signal-initiated power management method for a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2006-02-14 |
| 6978390 | Pipelined data processor with instruction-initiated power management control | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2005-12-20 |
| 6910141 | Pipelined data processor with signal-initiated power management control | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2005-06-21 |
| 6721894 | METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2004-04-13 |
| 6694443 | SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2004-02-17 |
| 6343363 | Method of invoking a low power mode in a computer system using a halt instruction | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2002-01-29 |
| 6088807 | Computer system with low power mode invoked by halt instruction | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 2000-07-11 |
| 5860111 | Coherency for write-back cache in a system designed for write-through cache including export-on-hold | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko +1 more | 1999-01-12 |
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko +1 more | 1997-09-02 |
| 5632037 | Microprocessor having power management circuitry with coprocessor support | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 1997-05-20 |
| 5630143 | Microprocessor with externally controllable power management | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 1997-05-13 |
| 5524234 | Coherency for write-back cache in a system designed for write-through cache including write-back latency control | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko +1 more | 1996-06-04 |
| 5375209 | Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin | Robert Maher, Raul A. Garibay, Jr., Mark Bluhm | 1994-12-20 |