Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9256548 | Rule-based virtual address translation for accessing data | Donald E. Steiss, John H. W. Bettink, John C. Carney, Mark W. Hervin | 2016-02-09 |
| 7421637 | Generating test input for a circuit | David Brian Koch Erickson | 2008-09-02 |
| 7116740 | Method and system for providing clock signals | — | 2006-10-03 |
| 7047432 | Method and system for synchronizing output from differently timed circuits | — | 2006-05-16 |
| 6122696 | CPU-peripheral bus interface using byte enable signaling to control byte lane steering | Andrew Brown | 2000-09-19 |
| 5898815 | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency | Mark Bluhm | 1999-04-27 |
| 5860111 | Coherency for write-back cache in a system designed for write-through cache including export-on-hold | Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1999-01-12 |
| 5742184 | Microprocessor having a compensated input buffer circuit | — | 1998-04-21 |
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1997-09-02 |
| 5611071 | Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture | — | 1997-03-11 |
| 5596731 | Single clock bus transfers during burst and non-burst cycles | Mark Bluhm | 1997-01-21 |
| 5524234 | Coherency for write-back cache in a system designed for write-through cache including write-back latency control | Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1996-06-04 |