DD

Douglas E. Duschatko

CI Cisco: 7 patents #2,018 of 13,007Top 20%
CY Cyrix: 4 patents #15 of 51Top 30%
NS National Semiconductor: 2 patents #867 of 2,238Top 40%
Overall (All Time): #354,934 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7551640 Method and apparatus for errorless frame timing adjustment Rudolph B. Klecka, III, Lane B. Quibodeaux, David D. Wilson 2009-06-23
6982974 Method and apparatus for a rearrangeably non-blocking switching matrix Ali Najib Saleh, Lane B. Quibodeaux 2006-01-03
6983414 Error insertion circuit for SONET forward error correction Andrew J. Thurston 2006-01-03
6973041 Path AIS insertion for concatenated payloads across multiple processors Lane B. Quibodeaux, Robert A. Hall, Andrew J. Thurston 2005-12-06
6934305 Method and apparatus for detecting errors in a backplane frame Lane B. Quibodeaux, Robert A. Hall, Andrew J. Thurston 2005-08-23
6801548 Channel ordering for communication signals split for matrix switching Lane B. Quibodeaux, Robert A. Hall, Andrew J. Thurston 2004-10-05
6735197 Concatenation detection across multiple chips Lane B. Quibodeaux, Robert A. Hall, Andrew J. Thurston 2004-05-11
5878269 High speed processor for operation at reduced operating voltage John K. Eitrheim, Richard B. Reis, Steve McMahan, Lawrence Henry Hudepohl, Tai Dinh Ngo +1 more 1999-03-02
5860111 Coherency for write-back cache in a system designed for write-through cache including export-on-hold Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Raul A. Garibay, Jr. +1 more 1999-01-12
5664149 Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Raul A. Garibay, Jr. +1 more 1997-09-02
5644788 Burst transfers using an ascending or descending only burst ordering David A. Courtright 1997-07-01
5572682 Control logic for a sequential data buffer using byte read-enable lines to define and shift the access window Raul A. Garibay, Jr. 1996-11-05
5524234 Coherency for write-back cache in a system designed for write-through cache including write-back latency control Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Raul A. Garibay, Jr. +1 more 1996-06-04
5146461 Memory error correction system distributed on a high performance multiprocessor bus and method therefor Nicholas P. Mati, Richard A. Herrington 1992-09-08