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System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic |
Qiujie Dong |
2012-05-08 |
| 7447982 |
BCH forward error correction decoder |
— |
2008-11-04 |
| 7366969 |
System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic |
Qiujie Dong |
2008-04-29 |
| 7227844 |
Non-standard concatenation mapping for payloads |
Robert A. Hall, Lane B. Quibodeaux |
2007-06-05 |
| 7124064 |
Automatic generation of hardware description language code for complex polynomial functions |
— |
2006-10-17 |
| 7003715 |
Galois field multiply accumulator |
— |
2006-02-21 |
| 6983414 |
Error insertion circuit for SONET forward error correction |
Douglas E. Duschatko |
2006-01-03 |
| 6973041 |
Path AIS insertion for concatenated payloads across multiple processors |
Douglas E. Duschatko, Lane B. Quibodeaux, Robert A. Hall |
2005-12-06 |
| 6934305 |
Method and apparatus for detecting errors in a backplane frame |
Douglas E. Duschatko, Lane B. Quibodeaux, Robert A. Hall |
2005-08-23 |
| 6801548 |
Channel ordering for communication signals split for matrix switching |
Douglas E. Duschatko, Lane B. Quibodeaux, Robert A. Hall |
2004-10-05 |
| 6738392 |
Method and apparatus of framing high-speed signals |
— |
2004-05-18 |
| 6735197 |
Concatenation detection across multiple chips |
Douglas E. Duschatko, Lane B. Quibodeaux, Robert A. Hall |
2004-05-11 |
| 6684350 |
Repetitive pattern testing circuit for AC-coupled systems |
James T. Theodoras, II, Daniel Lee Chaplin |
2004-01-27 |