Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7711926 | Mapping system and method for instruction set processing | Ryan C. Kinter | 2010-05-04 |
| 6742165 | System, method and computer program product for web-based integrated circuit design | Lavi A. Lev, John Knowles, Darren M. Jones | 2004-05-25 |
| 6651156 | Mechanism for extending properties of virtual memory pages by a TLB | Lawrence Henry Hudepohl, Kevin D. Kissell, G. Michael Uhler | 2003-11-18 |
| 6493776 | Scalable on-chip system bus | Vidya Rajagopalan, Radhika Thekkath, G. Michael Uhler | 2002-12-10 |
| 6430655 | Scratchpad RAM memory accessible in parallel to a primary cache | Ryan C. Kinter | 2002-08-06 |
| 5892249 | Integrated circuit having reprogramming cell | David L. Trawick | 1999-04-06 |
| 5860111 | Coherency for write-back cache in a system designed for write-through cache including export-on-hold | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1999-01-12 |
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1997-09-02 |
| 5644788 | Burst transfers using an ascending or descending only burst ordering | Douglas E. Duschatko | 1997-07-01 |
| 5524234 | Coherency for write-back cache in a system designed for write-through cache including write-back latency control | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1996-06-04 |
| 5010559 | System for synchronizing data frames in a serial bit stream | James T. O'Connor | 1991-04-23 |
| 5005191 | System for synchronizing data frame groups in a serial bit stream | James T. O'Connor | 1991-04-02 |