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Data cache virtual hint way prediction, and applications thereof |
Meng-Bing Yu, Era K. Nangia, Michael Ni |
2015-07-28 |
| 8078846 |
Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated |
Karagada Ramarao Kishore, Xing Yu Jiang, Maria Ukanwa |
2011-12-13 |
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Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses |
Radhika Thekkath, Karagada Ramarao Kishore, Kevin D. Kissell |
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Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
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2010-05-04 |
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Data cache virtual hint way prediction, and applications thereof |
Meng-Bing Yu, Era K. Nangia, Michael Ni |
2009-09-22 |
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System and method to trace high performance multi-issue processors |
Radhika Thekkath, Franz Treue, Søren Kragh |
2007-01-02 |
| 7124072 |
Program counter and data tracing from a multi-issue processor |
Radhika Thekkath, George Michael Uhler, Franz Treue, Lawrence Henry Hudepohl |
2006-10-17 |
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Low latency system bus interface for multi-master processing environments |
Adel Alsaadi |
2004-05-04 |
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Scalable on-chip system bus |
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2002-12-10 |
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Method and apparatus for controlling a rounding operation in a floating point multiplier circuit |
William C. Madden, Sridhar Samudrala |
1994-08-23 |
| 5155382 |
Two-stage CMOS latch with single-wire clock |
William C. Madden |
1992-10-13 |