EN

Era K. Nangia

NV NVIDIA: 6 patents #1,173 of 7,811Top 20%
MT Mips Technologies: 6 patents #36 of 129Top 30%
Apple: 2 patents #9,168 of 18,612Top 50%
DE Digital Equipment: 2 patents #602 of 2,100Top 30%
IBM: 2 patents #32,839 of 70,183Top 50%
Overall (All Time): #245,255 of 4,157,543Top 6%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12253913 Memory error tracking and logging Farid Nemati, Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, James Vash +1 more 2025-03-18
11934265 Memory error tracking and logging Farid Nemati, Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, James Vash +1 more 2024-03-19
10768939 Load/store unit for a processor, and applications thereof Meng-Bing Yu, Michael Ni 2020-09-08
10430340 Data cache virtual hint way prediction, and applications thereof Meng-Bing Yu, Michael Ni 2019-10-01
10268481 Load/store unit for a processor, and applications thereof Meng-Bing Yu, Michael Ni 2019-04-23
10108548 Processors and methods for cache sparing stores Ranjit J. Rozario, Debasish Chandra, Ranganathan Sudhakar 2018-10-23
9946547 Load/store unit for a processor, and applications thereof Meng-Bing Yu, Michael Ni 2018-04-17
9632939 Data cache virtual hint way prediction, and applications thereof Meng-Bing Yu, Michael Ni, Karagada Ramarao Kishore 2017-04-25
9092343 Data cache virtual hint way prediction, and applications thereof Meng-Bing Yu, Michael Ni, Vidya Rajagopalan 2015-07-28
7769958 Avoiding livelock using intervention messages in multiple core processors Ryan C. Kinter 2010-08-03
7594079 Data cache virtual hint way prediction, and applications thereof Meng-Bing Yu, Michael Ni, Vidya Rajagopalan 2009-09-22
7543207 Full scan solution for latched-based design Lew G. Chua-Eoan 2009-06-02
7246287 Full scan solution for latched-based design Lew G. Chua-Eoan 2007-07-17
6883156 Apparatus and method for relative position annotation of standard cell components to facilitate datapath design Alex Khainson, Donald C. Ramsey, Jr., Lew G. Chua-Eoan 2005-04-19
5860150 Instruction pre-fetching of a cache line within a processor Kevin Arthur Chiarot, Michael John Mayfield, Milford John Peterson 1999-01-12
5796976 Temporary storage having entries smaller than memory bus Bhavin Shah, Gilbert M. Wolrich, Nital Patwa 1998-08-18
5721864 Prefetching instructions between caches Kevin Arthur Chiarot, Michael John Mayfield, Milford John Peterson 1998-02-24
5418973 Digital computer system with cache controller coordinating both vector and scalar operations James P. Ellis, Nital Patwa, Bhavin Shah, Gilbert M. Wolrich 1995-05-23