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USPTO Patent Rankings Data through Dec 31, 2025
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Ryan C. Kinter — 29 Patents

MTMips Technologies: 29 patents #4 of 129Top 4%
Mountain View, CA: #638 of 11,022 inventorsTop 6%
California: #18,137 of 386,348 inventorsTop 5%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
Ryan C. Kinter has been granted 29 US patents while listed as an inventor at Mips Technologies. The first was granted in 2002 and the most recent in September 2020. Ryan C. Kinter ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list Ryan C. Kinter in Mountain View, CA, US.

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10782977 Fault detecting and fault tolerant multi-threaded processors Timothy Charles Mace 2020-09-22
8392663 Coherent instruction cache utilizing cache-op execution resources Darren M. Jones, Matthias Knoth 2013-03-05
8230202 Apparatus and method for condensing trace information in a multi-processor system Thomas B. Berg, Jaidev P. Patwardhan, Radhika Thekkath 2012-07-24 $2,463,000
8151268 Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency Darren M. Jones, Michael Gottlieb Jensen, Sanjay Vishin 2012-04-03 $2,050,000
8131941 Support for multiple coherence domains 2012-03-06 $4,318,000
7925859 Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor Soumya Banerjee, Michael Gottlieb Jensen 2011-04-12 $2,509,000
7873810 Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion Darren M. Jones, Radhika Thekkath, Chinh Tran 2011-01-18 $5,473,000
7853777 Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions Darren M. Jones, G. Michael Uhler, Sanjay Vishin 2010-12-14 $9,487,000
7769958 Avoiding livelock using intervention messages in multiple core processors Era K. Nangia 2010-08-03 $963,000
7752627 Leaky-bucket thread scheduler in a multithreading microprocessor Darren M. Jones, Thomas A. Petersen, Sanjay Vishin 2010-07-06 $2,140,000
7739455 Avoiding livelock using a cache manager in multiple core processors Sanjay Vishin 2010-06-15 $1,129,000
7711926 Mapping system and method for instruction set processing David A. Courtright 2010-05-04 $562,000
7707389 Multi-ISA instruction fetch unit for a processor, and applications thereof Soumya Banerjee, John Kelley 2010-04-27 $1,243,000
7681014 Multithreading instruction scheduler employing thread group priorities Michael Gottlieb Jensen 2010-03-16 $2,120,000
7664936 Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages Michael Gottlieb Jensen, Darren M. Jones, Sanjay Vishin 2010-02-16 $1,095,000
7660969 Multithreading instruction scheduler employing thread group priorities Michael Gottlieb Jensen 2010-02-09 $960,000
7657891 Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency Michael Gottlieb Jensen, Darren M. Jones, Sanjay Vishin 2010-02-02 $724,000
7657708 Methods for reducing data cache access power in a processor using way selection bits Matthias Knoth 2010-02-02 $724,000
7650465 Micro tag array having way selection bits for reducing data cache access power Matthias Knoth 2010-01-19 $1,098,000
7634619 Method and apparatus for redirection of operations between interfaces Gideon Intrater, Anders M. Jagd 2009-12-15 $1,595,000
7627794 Apparatus and method for discrete test access control of multiple cores 2009-12-01 $1,514,000
7613904 Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler Darren M. Jones, Kevin D. Kissell, Thomas A. Petersen 2009-11-03 $1,670,000
7594089 Smart memory based synchronization controller for a multi-threaded multiprocessor SoC Sanjay Vishin, Kevin D. Kissell, Darren M. Jones 2009-09-22 $1,617,000
7558939 Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor Soumya Banerjee, Michael Gottlieb Jensen 2009-07-07 $2,395,000
7509456 Apparatus and method for discovering a scratch pad memory configuration Scott M. McCoy, Gideon Intrater 2009-03-24 $792,000