Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10782977 | Fault detecting and fault tolerant multi-threaded processors | Timothy Charles Mace | 2020-09-22 |
| 8392663 | Coherent instruction cache utilizing cache-op execution resources | Darren M. Jones, Matthias Knoth | 2013-03-05 |
| 8230202 | Apparatus and method for condensing trace information in a multi-processor system | Thomas B. Berg, Jaidev P. Patwardhan, Radhika Thekkath | 2012-07-24 |
| 8151268 | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency | Darren M. Jones, Michael Gottlieb Jensen, Sanjay Vishin | 2012-04-03 |
| 8131941 | Support for multiple coherence domains | — | 2012-03-06 |
| 7925859 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor | Soumya Banerjee, Michael Gottlieb Jensen | 2011-04-12 |
| 7873810 | Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion | Darren M. Jones, Radhika Thekkath, Chinh Tran | 2011-01-18 |
| 7853777 | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions | Darren M. Jones, G. Michael Uhler, Sanjay Vishin | 2010-12-14 |
| 7769958 | Avoiding livelock using intervention messages in multiple core processors | Era K. Nangia | 2010-08-03 |
| 7752627 | Leaky-bucket thread scheduler in a multithreading microprocessor | Darren M. Jones, Thomas A. Petersen, Sanjay Vishin | 2010-07-06 |
| 7739455 | Avoiding livelock using a cache manager in multiple core processors | Sanjay Vishin | 2010-06-15 |
| 7711926 | Mapping system and method for instruction set processing | David A. Courtright | 2010-05-04 |
| 7707389 | Multi-ISA instruction fetch unit for a processor, and applications thereof | Soumya Banerjee, John Kelley | 2010-04-27 |
| 7681014 | Multithreading instruction scheduler employing thread group priorities | Michael Gottlieb Jensen | 2010-03-16 |
| 7664936 | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages | Michael Gottlieb Jensen, Darren M. Jones, Sanjay Vishin | 2010-02-16 |
| 7660969 | Multithreading instruction scheduler employing thread group priorities | Michael Gottlieb Jensen | 2010-02-09 |
| 7657891 | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency | Michael Gottlieb Jensen, Darren M. Jones, Sanjay Vishin | 2010-02-02 |
| 7657708 | Methods for reducing data cache access power in a processor using way selection bits | Matthias Knoth | 2010-02-02 |
| 7650465 | Micro tag array having way selection bits for reducing data cache access power | Matthias Knoth | 2010-01-19 |
| 7634619 | Method and apparatus for redirection of operations between interfaces | Gideon Intrater, Anders M. Jagd | 2009-12-15 |
| 7627794 | Apparatus and method for discrete test access control of multiple cores | — | 2009-12-01 |
| 7613904 | Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler | Darren M. Jones, Kevin D. Kissell, Thomas A. Petersen | 2009-11-03 |
| 7594089 | Smart memory based synchronization controller for a multi-threaded multiprocessor SoC | Sanjay Vishin, Kevin D. Kissell, Darren M. Jones | 2009-09-22 |
| 7558939 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor | Soumya Banerjee, Michael Gottlieb Jensen | 2009-07-07 |
| 7509456 | Apparatus and method for discovering a scratch pad memory configuration | Scott M. McCoy, Gideon Intrater | 2009-03-24 |