Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9141545 | Speculative read in a cache coherent microprocessor | William Lee | 2015-09-22 |
| 8930634 | Speculative read in a cache coherent microprocessor | William Lee | 2015-01-06 |
| 8230202 | Apparatus and method for condensing trace information in a multi-processor system | Ryan C. Kinter, Jaidev P. Patwardhan, Radhika Thekkath | 2012-07-24 |
| 8001283 | Efficient, scalable and high performance mechanism for handling IO requests | William Lee | 2011-08-16 |
| 7552247 | Increased computer peripheral throughput by using data available withholding | Adrian C. Moga, Dale Beyer | 2009-06-23 |
| 7124410 | Distributed allocation of system hardware resources for multiprocessor systems | Bruce M. Gilbert, Stacey G. Lloyd | 2006-10-17 |
| 7093257 | Allocation of potentially needed resources prior to complete transaction receipt | Stacey G. Lloyd | 2006-08-15 |
| 6973544 | Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system | Bruce M. Gilbert, Thomas D. Lovett | 2005-12-06 |
| 6807586 | Increased computer peripheral throughput by using data available withholding | Adrian C. Moga, Dale Beyer | 2004-10-19 |
| 6795889 | Method and apparatus for multi-path data storage and retrieval | Wayne A. Downer, Thomas Kloos, Richard Stout | 2004-09-21 |
| 6785779 | Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture | Stacey G. Lloyd | 2004-08-31 |
| 6598120 | Assignment of building block collector agent to receive acknowledgments from other building block agents | Bruce M. Gilbert | 2003-07-22 |
| 6591370 | Multinode computer system with distributed clock synchronization system | Thomas D. Lovett, Bruce M. Gilbert | 2003-07-08 |
| 5916314 | Method and apparatus for cache tag mirroring | Tapas Datta | 1999-06-29 |
| 5261057 | I/O bus to system interface | Richard W. Coyle, Zenja Chao | 1993-11-09 |
| 5003463 | Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus | Richard W. Coyle, Zenja Chao | 1991-03-26 |