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Speculative read in a cache coherent microprocessor |
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Speculative read in a cache coherent microprocessor |
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2015-01-06 |
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Apparatus and method for condensing trace information in a multi-processor system |
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Efficient, scalable and high performance mechanism for handling IO requests |
William Lee |
2011-08-16 |
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Increased computer peripheral throughput by using data available withholding |
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2009-06-23 |
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Distributed allocation of system hardware resources for multiprocessor systems |
Bruce M. Gilbert, Stacey G. Lloyd |
2006-10-17 |
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Allocation of potentially needed resources prior to complete transaction receipt |
Stacey G. Lloyd |
2006-08-15 |
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Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system |
Bruce M. Gilbert, Thomas D. Lovett |
2005-12-06 |
| 6807586 |
Increased computer peripheral throughput by using data available withholding |
Adrian C. Moga, Dale Beyer |
2004-10-19 |
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Method and apparatus for multi-path data storage and retrieval |
Wayne A. Downer, Thomas Kloos, Richard Stout |
2004-09-21 |
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Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture |
Stacey G. Lloyd |
2004-08-31 |
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Assignment of building block collector agent to receive acknowledgments from other building block agents |
Bruce M. Gilbert |
2003-07-22 |
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Multinode computer system with distributed clock synchronization system |
Thomas D. Lovett, Bruce M. Gilbert |
2003-07-08 |
| 5916314 |
Method and apparatus for cache tag mirroring |
Tapas Datta |
1999-06-29 |
| 5261057 |
I/O bus to system interface |
Richard W. Coyle, Zenja Chao |
1993-11-09 |
| 5003463 |
Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus |
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1991-03-26 |