| 7406632 |
Error reporting network in multiprocessor computer |
Charles Sealey, John Lynch, Mark S. Myers, Jason J. Lewis, Paul Kayfes |
2008-07-29 |
| 7237100 |
Transaction redirection mechanism for handling late specification changes and design errors |
— |
2007-06-26 |
| 7124410 |
Distributed allocation of system hardware resources for multiprocessor systems |
Thomas B. Berg, Bruce M. Gilbert |
2006-10-17 |
| 7093257 |
Allocation of potentially needed resources prior to complete transaction receipt |
Thomas B. Berg |
2006-08-15 |
| 6785779 |
Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture |
Thomas B. Berg |
2004-08-31 |
| 5787095 |
Multiprocessor computer backlane bus |
Mark S. Myers, Richard Stout, Robert Takasumi, John Lynch |
1998-07-28 |
| 5581713 |
Multiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitration |
Mark S. Myers, Richard Stout, Robert Takasumi, John Lynch |
1996-12-03 |
| 4912631 |
Burst mode cache with wrap-around fill |
— |
1990-03-27 |
| 4860322 |
Anti-clock skew distribution apparatus |
— |
1989-08-22 |
| 4808855 |
Distributed precharge wire-or bus |
— |
1989-02-28 |
