| 8151268 |
Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency |
Darren M. Jones, Ryan C. Kinter, Sanjay Vishin |
2012-04-03 |
| 8151093 |
Software programmable hardware state machines |
Soumya Banerjee, Gideon Intrater |
2012-04-03 |
| 8078840 |
Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states |
Soumya Banerjee |
2011-12-13 |
| 7990989 |
Transaction selector employing transaction queue group priorities in multi-port switch |
— |
2011-08-02 |
| 7961745 |
Bifurcated transaction selector supporting dynamic priorities in multi-port switch |
— |
2011-06-14 |
| 7925859 |
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor |
Soumya Banerjee, Ryan C. Kinter |
2011-04-12 |
| 7773621 |
Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch |
— |
2010-08-10 |
| 7760748 |
Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch |
— |
2010-07-20 |
| 7681014 |
Multithreading instruction scheduler employing thread group priorities |
Ryan C. Kinter |
2010-03-16 |
| 7664936 |
Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages |
Darren M. Jones, Ryan C. Kinter, Sanjay Vishin |
2010-02-16 |
| 7660969 |
Multithreading instruction scheduler employing thread group priorities |
Ryan C. Kinter |
2010-02-09 |
| 7657883 |
Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor |
— |
2010-02-02 |
| 7657891 |
Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency |
Darren M. Jones, Ryan C. Kinter, Sanjay Vishin |
2010-02-02 |
| 7634638 |
Instruction encoding for system register bit set and clear |
— |
2009-12-15 |
| 7631130 |
Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor |
— |
2009-12-08 |
| 7600100 |
Instruction encoding for system register bit set and clear |
— |
2009-10-06 |
| 7558939 |
Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor |
Soumya Banerjee, Ryan C. Kinter |
2009-07-07 |
| 7509447 |
Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor |
— |
2009-03-24 |
| 7509480 |
Selection of ISA decoding mode for plural instruction sets based upon instruction address |
Morten Stribaek |
2009-03-24 |
| 7506140 |
Return data selector employing barrel-incrementer-based round-robin apparatus |
— |
2009-03-17 |
| 7490230 |
Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor |
Soumya Banerjee |
2009-02-10 |
| 7149878 |
Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values |
Morten Stribaek |
2006-12-12 |